Virtual class and virtual method

SystemVerilog
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1

As I understand, virtual qualifier for a class ensures that it cannot be instantiated and hence it becomes an abstract class.
Virtual qualifier for a function ensures late binding feature to support OOPS and polymorphism.

Is my understanding correct?

2

In reply to verif_learner:
Yes, SystemVerilog likes to reuse keywords. There is also a virtual interface which has nothing to do with OOP.