HI Dave,
I have a VHDL model, which contains VHDL record as parameter, I am trying to integrate the model into SV environment. I converted VHDL record parameter into struct in my sv code as shown below. I am getting below error.Can you please let me know is there any possibility to connect VHDL record parameter to the SV code.
Error :
xmelab: *E,CFIGTC (model_tb.sv): VHDL generic model.config model.vhd) type is not compatible with Verilog.
.config (tb_config)
|
xrun: *E,ELBERR: Error during elaboration (status 1), exiting.
code :
TYPE rtl_config is
RECORD
path : string ;
x : STD_LOGIC ;
y : STD_LOGIC_VECTOR(1 DOWNTO 0);
z : INTEGER_ARRAY(1 DOWNTO 0);
END RECORD ;
model (cfg : rtl_config)
PORT ( A : IN STD_LOGIC ;
B : OUT STD_LOGIC )
end model ;
module model_tb ;
bit a,b;
typedef struct { is
string path ;
bit x ;
bit [1:0] y ;
bit z [1:0];
} tb_config_tb_t
tb_config_tb_t tb_config ;
model #(.cfg(tb_config))
model_inst(.a(a),
.b(b));
endmodule : model_tb
Regards,
Jayaprakash