VHDL port connect to systemverilog

SystemVerilog
,
1

There is a VHDL IP:

type record_port_type is record
    i_data : std_logic_vector(31 downto 0);
    o_data : std_logic_vector(31 downto 0);
end record;
entity src_vhd is
port (
    data_port : inout record_port_type;
);
end entity src_vhd;

Question :
How to connect the data_port to sv?

2

In reply to cainiaoma:

Unfortunately there is no standard for communication between different standards. You need to read the user manual of your tool to see how a VHDL record maps to a struct in SystemVerilog.

3

In reply to dave_59:

Thanks for your help.I find the way in Chaper9 Questasim user manual.