VHDL package in verilog/SV

SystemVerilog
1

Hi,
Can anybody help me , how can we use the VHDL package(userdefined) in Verilog/SV testbench(In Cadnace IES)

Thanks,
Aslam

2

The 1800 SystemVerilog LRM is totally unaware of VHDL; the term “VHDL” is ot even mentioned.
Tools support multi-language simulation, and this is the only way I know of using a VHDL package within a SystemVerilog environment. That means that to use the package, you would need an entity/architecture that has access to the package. Interaction from the SystemVerilog to VHDL would then be through ports. It’s messy!

Why not convert the VHDL package to SystemVerilog?

Ben Cohen, Design and verification expert (310) 997-2187
http://www.systemverilog.us/ ben@systemverilog.us

  • SystemVerilog Assertions Handbook, 2nd Edition, 2010 ISBN 878-0-9705394-8-7
  • A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
  • Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
  • Component Design by Example, 2001 ISBN 0-9705394-0-1
  • VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
  • VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115