VHDL code Latch inferring Issue

SystemVerilog
1

Hello all,
I am design engineer, When i am trying to synthesize the below code its inferring the latch for data split .
Any one who has hang on VHDL, Please help me out .
I am using rc compiler for synthesize. The error info given below.
Code:

data : std_logic_vector(7 downto 0); --input port in entity
signal wraddress_d : std_logic_vector(1 downto 0);
signal data_splt : std_logic_vector(31 downto 0);

process(wraddress_d,data)

begin

    case wraddress_d is
        when "00"=> data_splt(7 downto 0)  <=  data; 
        when "01"=> data_splt(15 downto 8) <=  data;
        when "10"=> data_splt(23 downto 16)<=  data;
        when "11"=> data_splt(31 downto 24)<=  data;
        when others => data_splt <= (others => '0');
    end case;
    end process;

Latch inferred. [CDFG2G-616]
: Latch inferred for variable ‘data_splt’ in file ‘/space/ips/govilb/bt656/rtl/ram2.vhd’

2

Ravi,
The array of 32 bits shall be fully assigned under all cases to avoid latches. Looks like you need some MUX-ing logic here, ask yourself/specification -

when “00”=> data_splt(7 downto 0) <= data;

– What happens to data_splt (31 downto 8) in this case?

HTH
Ajeetha, CVC