In reply to bhajanpreetsinght:
In reply to dave_59:
I showed the simulation snap, where it show passes and fails please see the image
Hi Dave,
Please nswer I gave all scenarios
code is below
property p2;
@(posedge Clk) disable iff( (reset==0))
(a) |-> lock3 within (a==1);
endproperty
P2: assert property(p2)
else begin
uvm_pkg::uvm_report_error(“assertions”, "Error on assertion " );
end
where lock3 is logic lock3;
always@(posedge clk)
begin
if (A==0| reset==0)
lock3<=0;
else
lock3<=(b|c);
end
expectation is if a is higha t 7 ns to 15ns, bis high at 9 ns and c is not high ,as we want to check during a is high which is from 15 ns-7 ns=8ns and be is high just after two clock edge of a and falls in between when a is high, it should show pass at 15 ns
similarly if neither b or c are high in between 7 to 15 ns ,i t should throw false at 15 ns
note b or c can toggle as many times in between a going high and reamin high we are only concerned with one toggle
Hope it clears now