Verilog vs SV

In reply to Design Engineer:

Hi,

Until and unless, you find the new keywords/constructs (which belongs to systemverilog) like logic, always_ff, always_comb,enum, struct, definition of functions/tasks without begin/end keywords, threads like join_any, join_none, semaphore (the list continues), you cannot differentiate verilog and systemverilog codes. What ever the program that you have written using verilog keywords can be saved with .v as well as .sv extention.
Hope this helps.
PuttaSatish