In reply to Design Engineer:
Verilog and SystemVerilog are the same language. There is one IEEE specification that defines the language. SystemVerilog and Verilog were originally defined by two separate standards, but that is no longer the case.
In reply to Design Engineer:
Verilog and SystemVerilog are the same language. There is one IEEE specification that defines the language. SystemVerilog and Verilog were originally defined by two separate standards, but that is no longer the case.