Verilog syntax question

SystemVerilog
,
1

Hello,

I came across this colon syntax : in Verilog literature. I think it might be a typo and was intended to be a semicolon ; ??

example,

initial begin
signal_assignment_1
:
end

any feedback is appreciated
-Glen

2

In reply to glenh81:

There no legal syntax that would have
: before an
end keyword. Without knowing what
signal_assignment_1 represents, it’s hard to know what the intent was.

It’s also possible they meant a vertical ellipsis and missed a dot.

initial begin
   signal_assignment_1
   ⋮
end