Verilog Operators

SystemVerilog
1

assign c = z & ~(a|b); (Does this become z nand (a|b); ? )
assign c = z & (~(a|b));
Is there a difference in logic?

2

In reply to abhi9891:

Verilog only has unary NAND, which is written as ~&(expression). So there should be no difference in the two assignemnts. Did you try it?