Verilog blocking/nonblocking assignment in clk generator with self triggered

SystemVerilog
,
1

Why the following code is not self-triggered?

module osc1 (clk);
output clk;
reg clk;
initial #10 clk = 0;
always @(clk) #10 clk = ~clk;

always
begin
$monitor(“%0d clk=%0d\n”,$time,clk);
#100 $finish;
end
endmodule
output:

0 clk=x

10 clk=0

20 clk=1

when used non-blocking assignment it works normally i.e., always @(clk) #10 clk <= ~clk;

output:

0 clk=x

10 clk=0

20 clk=1

30 clk=0

40 clk=1

50 clk=0

60 clk=1

70 clk=0

80 clk=1

90 clk=0

thanks in advance.

2

hi,
@clk and #10 clk = ~clk is blocking assignment, the two statement are scheduled at Active region,
but @clk and #10 clk <= ~clk, the first statement is scheduled at Active region and the sencond is scheduled at NBA region, when clk <= ~clk hanpen, the toggle of clk will reactive the @clk hanppen, and periodic trigger the non-blocking statement.

the generally writing style like below:

always #10 clk = ~clk; or
always #10 clk <= ~clk;

ps:no @clk condition

Thanks a lot!

3

In reply to N Raghava :

In case of blocking, the compiler goes back to the start of the always block after successful execution of " #10 clk = ~clk;" and wait for the event which never occurs. Where as in case of non blocking, the compiler goes back to the start of always block before the assignment which is done in NBA region.