In reply to bachan21:
You did not clearly say what do you want to verify. Inmy eyes testing the reset includes to check if all components/modules which are resettable did the reset. Checking only the reset signal if it becomes active can be checked using SV assertions.
And you do not need to implement the reset_phase.
For what you are doing a reset variable/flag is needed in the seq_item. If the reset flag is set you can start the reset task in your driver. There is no special reset test needed.