Verification Methodology

SystemVerilog
,
1

Hello All,

If someone ask you to implement a Verification Methodology or Verification Flow,
what are they expecting. I think it is to build

  1. runscript for RTL/Gate Simulation
  2. script to generate UVM Testbench
  3. Register Model Generation
  4. Code Coverage
  5. Functional Coverage
  6. Gate Level Simulation

What else come under the Verification Methodology

Thanks
JeffD

2

In reply to dvuvmsv:
Short answer: Yes to the above list, but there is more.
The Verification Methodology includes the WHAT to verify and the HOW to verify.

  • The WHAT includes functionality, corner cases, coverage (line and functionality), timing (delays, max frequency), gate/RTL functionality matching, power consideration when under low power mode with blocks unpowered, clock domain crossing (CDC)

  • the HOW includes languages and libraries (e.g., SystemVerilog with SVA and UVM), the tools (simulation, emulation, CDC, smart editors with code analysis, test vector generation,…), formal verification,

  • Verification Horizons, Dec 2019 Issue addresses
    Hardware Emulation, Deadlock, Portable Stimulus, clock domain crossing (CDC) verification

  • The use of Verification of low power UPF (Unified Power Format); UPF provides the necessary constructs to capture various power-related details at various levels of abstraction. It is simualtable.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr

  1. SVA Alternative for Complex Assertions
    Verification Horizons - March 2018 Issue | Verification Academy
  2. SVA: Package for dynamic and range delays and repeats | Verification Academy
  3. SVA in a UVM Class-based Environment
    SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy
3

Thanks Ben
JeffD