In reply to dvuvmsv:
Short answer: Yes to the above list, but there is more.
The Verification Methodology includes the WHAT to verify and the HOW to verify.
The WHAT includes functionality, corner cases, coverage (line and functionality), timing (delays, max frequency), gate/RTL functionality matching, power consideration when under low power mode with blocks unpowered, clock domain crossing (CDC)
the HOW includes languages and libraries (e.g., SystemVerilog with SVA and UVM), the tools (simulation, emulation, CDC, smart editors with code analysis, test vector generation,…), formal verification,
The use of Verification of low power UPF (Unified Power Format); UPF provides the necessary constructs to capture various power-related details at various levels of abstraction. It is simualtable.