Can you please explain the Verification Flow ? What are the steps an organisation follows before starting verification of IP/ASIC ? Just like we have ASIC Design Flow can you explain ASIC Verification Flow ?
In reply to nayan2208:
The verification flow might not be here right in this forum. But a few words regarding this.
The verification is in most cases more comprehensive than the design flow. It depends on your neeeds reuqirements. Verifcation does not commonly mean only simple simulation. There might be additional requirements for emulation, formal verification, clock-domain-crossing etc.
The common way to define your verification process is extract from your design specification a so-called verification specification. This document contains all the verification requirements, i.e. what you have to verify with which methods. This is the basis to develop your own verification flow.
In reply to chr_sue:
I need a generalised Flow Chart of Verification Plan that can be set as common ground for the Verification Engineer how he and his team can proceed with Verification.
In reply to chr_sue:
I need a generalised Flow Chart of Verification Plan that can be set as common ground for the Verification Engineer how he and his team can proceed with Verification.
In reply to nayan2208:
Please visit my website christoph-suehnel.de
Under resources you’ll find a verifcation template I use in my projects.