In reply to ben@SystemVerilog.us:
Mmh first of all, thank you so much for your patience with me. Really appreciating the fact that you’re doing everything that you can to lead me in the right direction.
By taking a look at your code example, I get why you’re suggesting me to use only one agent, because maybe in the Generator file I can randomize situation variable which is a typedef enum type and according to its value, I can do something in the case statement; like, if situation is == RD, then I am going to provide to the Driver Read_enable ==1, Write_enable==0 etc and basically I can do this for each case (correct me if I am wrong).
My problem with one Agent would be: how can I deal with the two asynchronous clocks in the interface, driver and monitor? Driver and Monitor work for sure with a clock signal, so how am I supposed to know which one to use? In my case, the Write_clock is faster than the read_clock, I cannot use the write_clock signal to drive the read signals to the interface from the Driver…does it make sense for you what I am trying to say? Hope it does
Thanks for the model for the counter, going to check it right now.