Vector bit slicing with changing range

SystemVerilog
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1

Hi,

I tried to do assignment of range of bits from one vector to another.
The range might differ, based on another argument to the function called rd_size.
Received next error:
*Error-[NCE] Non-constant expression
The following expression should be a constant.
Expression: _width
Source info: masked_data[orig_addr[3:0]*4 +: _width] = _temp[orig_addr[3:0]4 +: _width];

What elegant way one might use to code it, except moving the last statement of the function into each line of the case?


function bit [127:0] masked_data(input bit[127:0] data_line, input bit[33-1:0] orig_addr, input svt_axi_transaction::burst_size_enum rd_size);
    bit[127:0]  _temp = data_line;
    bit[7:0]    _width;

    case (rd_size) 
        svt_axi_transaction::BURST_SIZE_8BIT        : _width = 8;
        svt_axi_transaction::BURST_SIZE_16BIT       : _width = 16;
        svt_axi_transaction::BURST_SIZE_32BIT       : _width = 32;
        svt_axi_transaction::BURST_SIZE_64BIT       : _width = 64;
        svt_axi_transaction::BURST_SIZE_128BIT      : _width = 128;
        default                                     : `uvm_fatal(get_name(), "Illegal AXI burst_size!")
    endcase
    
    masked_data[orig_addr[3:0]*4 +: _width] = _temp[orig_addr[3:0]*4 +: _width];
endfunction : masked_data

Thanks!

2

In reply to Michael54:

You can use a for loop iterating over the number of bytes to transfer. (if you encoded rd_size correctly, it should be n_bytes = 2**rd_size

for(int i=0;i<n_bytes;i++) 
   masked_data[i+orig_addr[3:0]*4 +: 8] = data_line[i+orig_addr[3:0]*4 +: 8];