VCD dump

SystemVerilog
1

I want to generate vcd dump for a simulation and I want all signals including signals of submodules under design hierarchy top.d.dut_top.

I am getting some FATAL error in simulaiton when adding following verilog code:

initial begin
$dumpfile (“test.vcd”)
$dumpvars (0, top.d.dut_top);
end

I am unable to debug this and moved to do file option

I generated vcd by adding below lines to do file

vcd file test.vcd
vcd add /top/d/dut_top/*

The VCD file is generated successfully. But the dump only has signals at one level of hierarchy only i.e, top.d.dut_top and do not have the signals of submodules below top.d.dut_top hierarchy.

what is the do file command to mention that the vcd file should have dump for all signals, including signal of sub-modules under hierarchy top.d.dut_top. Or else, question is what is equivalent do file command line option corresponding to $dumpvars(0, top.d.dut_top);

Please help.

Regards,
San

2

The $dumpfile statement should end with semicolon.

3

Share compete FATAL Error and which tool do you use?

if you are using VCS then better you use below system task

initial begin
 $vpdplusfile("filename");
 $vpdpluson();
end