Variable visibility to various UVM components

In reply to tfitz:

You definitely wouldn’t want to get into anything structural, like analysis_ports

I want to clarify the above statement.

When ever I use analysis_ports it has always always been only transmitting “transactions”. My read_transaction has all the input variables and all the output variables. When I send an expected_read transaction packet from predictor to the scoreboard, I don’t assign values for each and every variables for the expected_read transaction, instead I only assign predicted values for the output and the remaining variables of the expected_read transaction packet are empty. I send this expected_read transaction - containing some filled and some blank - packet through the analysis port.

I thought can’t I just create another port and send just the required variables?

Questions:

  1. When you mention the statement above, are you telling creating such analysis ports (for variables instead of one complete transaction) it might cause more confusion?

  2. It’s not necessary that all variables of a transactions needs to have a value correct? I don’t why I think they should, but every time I send a partially filled transaction, I feel may be this might not be the right way of doing things.