Variable delay in $past(sig_name, vari_delay) assertion

SystemVerilog
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8

In reply to Nandeesha:

You can change the clocking within a property. Below is an example. I am showing you the approach, you should be able to work out the details


// o_c_500k changes at negedge of the clock and 
// ADC_START goes low at the posedge of the clock.
property P; 
    int v; 
    @(posedge clk) (1, , v=n) ##0 $fell(ADC_START) |->        
       strong(##1 $stable(ADC_START)  // (like your ",5" ",4"                      
              ##0 q_dynamic_delay(v) ##0 @(negedge clk) $changed(o_c_500k));
  // the q_dynamic_delay(v) is at the posedge clk  
endproperty 
  ap_P: assert property(P);  
  always @(negedge clk) 
  if (!randomize(n))`uvm_error("MYERR", "This is a randomize error");

Ben SystemVerilog.us