$changed(o_c_500k) |->($past($fell(ADC_START),delay_seq(o_c_500k_count+1))==1) && ($past($fell(ADC_START),delay_seq(o_c_500k_count))==0);
Couldn’t succeed. Please help me with this.
In your model, you seem to want to express something like
$changed(o_c_500k) |->($past($fell(ADC_START),var)==1) &&
($past($fell(ADC_START),var-1)==0);
// This is the wrong way to see or express an assertion. The recommended approach is the
// forward-looking. Thus, instead of saying
// BAD STYLE: If some_sequence_of_events then some_events must have happened in the past.
// BETTER STYLE: If some_events then other events now or in the future
// Something like
// Instead of
$changed(o_c_500k) |->($past($fell(ADC_START),5)==1) &&
($past($fell(ADC_START),4)==0);
// DO THIS
$fell(ADC_START) |-> strong(##1 $stable(ADC_START) // (like your ",5" ",4"
##[1:$] $changed(o_c_500k));
// $fell(ADC_START) |-> strong(##1 $stable(ADC_START) // (like your ",5" ",4"
// ##[1:$] $changed(o_c_500k));
import sva_delay_repeat_range_pkg::*;
int d1=30; // dynamic var set to 30
sequence my_sequence;
$changed(o_c_500k);
endsequence
$fell(ADC_START) |-> strong(##1 $stable(ADC_START) // (like your ",5" ",4"
##0 q_dynamic_delay(d1) ##0 my_sequence);
// OK too (the sequence is needed for other cases, see the package)
$fell(ADC_START) |-> strong(##1 $stable(ADC_START) // (like your ",5" ",4"
##0 q_dynamic_delay(d1) ##0 $changed(o_c_500k));
In your model, you seem to want to express something like
$changed(o_c_500k) |->($past($fell(ADC_START),var)==1) &&
($past($fell(ADC_START),var-1)==0);
// This is the wrong way to see or express an assertion. The recommended approach is the
// forward-looking. Thus, instead of saying
// BAD STYLE: If some_sequence_of_events then some_events must have happened in the past.
// BETTER STYLE: If some_events then other events now or in the future
// Something like
// Instead of
$changed(o_c_500k) |->($past($fell(ADC_START),5)==1) &&
($past($fell(ADC_START),4)==0);
// DO THIS
$fell(ADC_START) |-> strong(##1 $stable(ADC_START) // (like your ",5" ",4"
##[1:$] $changed(o_c_500k));
Hi Ben, thanks for your solution.
From your solution below, I see you’re checking from 1 to infinite cycle($).
$fell(ADC_START) |-> strong(##1stable(ADC_START) // (like your ",5" ",4"
##[1:] changed(o_c_500k));
But I need to check exactly after 'n' cycles. 'n' is through the register and has been randomized. It'll be keep on repeating in the loop. I can't check it from 1 to some cycles. And also, ‘n’ changes at negedge of the clock and ADC goes low at the posedge of the clock. So is there any way that I can sample at both the edges in the assertion. The $past works for only one value (i.e only if it’s hard coded).
import uvm_pkg::*; `include "uvm_macros.svh"
import sva_delay_repeat_range_pkg::*; // see above for package
module m;
int n; // dynamic var
// If n changes at the negedge clk, and you want to save that value before the fell of start
property P;
int v;
@(negedge clk) (1, , v=n) ##0 @(posedge clk)($fell(ADC_START)) |->
// consequent also @(posedge clk) because of flow through
strong(##1 $stable(ADC_START) // (like your ",5" ",4"
##0 q_dynamic_delay(v) ##0 $changed(o_c_500k));
ap_P: assert property(P);
always @(negedge clk)
if (!randomize(n))`uvm_error("MYERR", "This is a randomize error");
....
import uvm_pkg::*; `include "uvm_macros.svh"
import sva_delay_repeat_range_pkg::*; // see above for package
module m;
int n; // dynamic var
// If n changes at the negedge clk, and you want to save that value before the fell of start
property P;
int v;
@(negedge clk) (1, , v=n) ##0 @(posedge clk)($fell(ADC_START)) |->
// consequent also @(posedge clk) because of flow through
strong(##1 $stable(ADC_START) // (like your ",5" ",4"
##0 q_dynamic_delay(v) ##0 $changed(o_c_500k));
ap_P: assert property(P);
always @(negedge clk)
if (!randomize(n))`uvm_error("MYERR", "This is a randomize error");
....
In reply to ben@SystemVerilog.us:
Sorry, the o_c_500k changes at negedge of the clock. ‘n’ will be configured way before. Please ignore n.
o_c_500k changes at negedge of the clock and ADC_START goes low at the posedge of the clock. Since I couldn’t attach the timing diagram here, I have emailed it you your email ID. Please see you email for further clarification. Sorry for the inconvenience.
You can change the clocking within a property. Below is an example. I am showing you the approach, you should be able to work out the details
// o_c_500k changes at negedge of the clock and
// ADC_START goes low at the posedge of the clock.
property P;
int v;
@(posedge clk) (1, , v=n) ##0 $fell(ADC_START) |->
strong(##1 $stable(ADC_START) // (like your ",5" ",4"
##0 q_dynamic_delay(v) ##0 @(negedge clk) $changed(o_c_500k));
// the q_dynamic_delay(v) is at the posedge clk
endproperty
ap_P: assert property(P);
always @(negedge clk)
if (!randomize(n))`uvm_error("MYERR", "This is a randomize error");