In reply to Nandeesha:
In reply to ben@SystemVerilog.us:
Sorry, the o_c_500k changes at negedge of the clock. ‘n’ will be configured way before. Please ignore n.
o_c_500k changes at negedge of the clock and ADC_START goes low at the posedge of the clock. Since I couldn’t attach the timing diagram here, I have emailed it you your email ID. Please see you email for further clarification. Sorry for the inconvenience.