In reply to ben@SystemVerilog.us:
In reply to Nandeesha:
import uvm_pkg::*; `include "uvm_macros.svh"
import sva_delay_repeat_range_pkg::*; // see above for package
module m;
int n; // dynamic var
// If n changes at the negedge clk, and you want to save that value before the fell of start
property P;
int v;
@(negedge clk) (1, , v=n) ##0 @(posedge clk)($fell(ADC_START)) |->
// consequent also @(posedge clk) because of flow through
strong(##1 $stable(ADC_START) // (like your ",5" ",4"
##0 q_dynamic_delay(v) ##0 $changed(o_c_500k));
ap_P: assert property(P);
always @(negedge clk)
if (!randomize(n))`uvm_error("MYERR", "This is a randomize error");
....
Does this answer the requirements?
Ben SystemVerilog.us
Sorry, the o_c_500k changes at negedge of the clock. ‘n’ will be configured way before. Please ignore n.