In reply to ben@SystemVerilog.us:
In reply to Nandeesha:
As you know, the expressions in $past must be static; it cannot be a variable or a sequence.
$past( expression1 [, number_of_ticks] [, expression2] [, clocking_event])
In your model, you seem to want to express something like
$changed(o_c_500k) |->($past($fell(ADC_START),var)==1) &&
($past($fell(ADC_START),var-1)==0);
// This is the wrong way to see or express an assertion. The recommended approach is the
// forward-looking. Thus, instead of saying
// BAD STYLE: If some_sequence_of_events then some_events must have happened in the past.
// BETTER STYLE: If some_events then other events now or in the future
// Something like
// Instead of
$changed(o_c_500k) |->($past($fell(ADC_START),5)==1) &&
($past($fell(ADC_START),4)==0);
// DO THIS
$fell(ADC_START) |-> strong(##1 $stable(ADC_START) // (like your ",5" ",4"
##[1:$] $changed(o_c_500k));
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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Hi Ben, thanks for your solution.
From your solution below, I see you’re checking from 1 to infinite cycle($).
$fell(ADC_START) |-> strong(##1 stable(ADC_START) // (like your ",5" ",4"
##[1:] changed(o_c_500k));
But I need to check exactly after 'n' cycles. 'n' is through the register and has been randomized. It'll be keep on repeating in the loop. I can't check it from 1 to some cycles. And also, ‘n’ changes at negedge of the clock and ADC goes low at the posedge of the clock. So is there any way that I can sample at both the edges in the assertion. The $past works for only one value (i.e only if it’s hard coded).