In reply to ben@SystemVerilog.us:
In you need a var delay between $fell(ADC_START) and $changed(o_c_500k)
consider using my package at
https://verificationacademy.com/forums/systemverilog/sva-package-dynamic-and-range-delays-and-repeats
Thus,
// $fell(ADC_START) |-> strong(##1 $stable(ADC_START) // (like your ",5" ",4"
// ##[1:$] $changed(o_c_500k));
import sva_delay_repeat_range_pkg::*;
int d1=30; // dynamic var set to 30
sequence my_sequence;
$changed(o_c_500k);
endsequence
$fell(ADC_START) |-> strong(##1 $stable(ADC_START) // (like your ",5" ",4"
##0 q_dynamic_delay(d1) ##0 my_sequence);
// OK too (the sequence is needed for other cases, see the package)
$fell(ADC_START) |-> strong(##1 $stable(ADC_START) // (like your ",5" ",4"
##0 q_dynamic_delay(d1) ##0 $changed(o_c_500k));
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
- SVA Alternative for Complex Assertions
Verification Horizons - March 2018 Issue | Verification Academy - SVA: Package for dynamic and range delays and repeats | Verification Academy
- SVA in a UVM Class-based Environment
SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy