Variable Declaration inside Function

SystemVerilog
1

In Scenario 1/3 , the output value of c considers the value of input a and b passed during function call.
But , In Scenario 2 , the output value of c doesn’t consider the value of input a and b passed during function call .

Scenario 1 :

module mm;
  function int s;
    input int a;
    input int b ;
    int c ;  //= a+b;
    c= a+b;
    $display("a=%d -- b=%d --  c=%d ",a,b,c);
    return c;
  endfunction
  initial 
    $display ("-------------- %d",s(9,11));  
endmodule

Result is :
a= 9 – b= 11 – c= 20
-------------- 20
Scenario 2 :

module mm;
  function int s;
    input int a;
    input int b ;
    int c = a+b;
    //c= a+b;
    $display("a=%d -- b=%d --  c=%d ",a,b,c);
    return c;
  endfunction
  initial 
    $display ("-------------- %d",s(9,11));  
endmodule

Result is :
a= 9 – b= 11 – c= 0
-------------- 0

Scenario 3 :

module mm;
  function automatic int s;
    input int a;
    input int b ;
    int c = a+b;
    //c= a+b;
    $display("a=%d -- b=%d --  c=%d ",a,b,c);
    return c;
  endfunction
  initial 
    $display ("-------------- %d",s(9,11));  
endmodule

Result is :
a= 9 – b= 11 – c= 20
-------------- 20

Kindly justify .

Thanks in advance .
Best Regards,
Pranoy

2

In reply to PR359708:

In modules, functions are static by default, meaning variables declared in them will be static variables. So, in scenarios 1 & 2, the function is static. Consequently, the initialization in scenario 2 is only executed once (it is a static initialization completed before your initial block executes). In scenario 1, the variable is also static, but you using are procedurally computing the value when the function is called. In scenario 3, variable c is an automatic variable, so the initialization executes on every function call.

To make the effect more obvious, try converting this function into some kind of recursive function that calls itself, eg.

module mm;
  function int s;
    input int a;
    input int b ;
    int c = a+b;
    //c= a+b;
    if ( a > 0 ) s( a-1, b);
    $display("a=%d -- b=%d --  c=%d ",a,b,c);
    return c;
  endfunction

This will demonstrate the problem more clearly.

3

In reply to warnerrs:

The code you (and scenario 2) wrote was made illegal in the 1800-2012 LRM for the exact reason you are trying to explain. You should get an error if you try to initialize an implicitly static variable where the user has a choice of making it automatic. You need to declare it explicit static, or there are a number of ways of making it automatic.