In reply to dvuvmsv:
Hello,
I have a PLL Model in Verilog which has
parameter base_frequency = 1.5 ( 1.5 GHz )
parameter step_size = 0.040 ( 40 MHz )
Is it possible to use $valueplusargs and pass command line values and change the
paramter. I need to have different base frequency values and different step size values to be
passed
run_command +base_freq=1.7 +step_size=0.050
Thanks
JeffD
We cannot change the verilog parameter in run-time simulation using $value$plusargs.
The parameter is constant and only can be assigned in compile-time with default value, or elaboration-time with overriden value