#value/zero inside an always block

SystemVerilog
,
1

I faced an issue where the simulation hangs because of the following scenario (Note the real variable called var1 is not initialized anywhere)

module m1;
   real var1;
   bit clk =0;
   always begin
      #(1e5/var); 
      clk = ~clk;
   end
endmodule

After a quick investigation, I found out that the #(value/0) is evaluated as zero in the # context and is evaluated as 0 or x regarding 2-state or 4-state context it exists. so the clk is toggling too slow (I believe with delay equals the precision which is the smallest simulation time). This causes the simulation to propagate with extremely small time so it takes too long to reach the next evaluation which is scheduled after a large time compared to the delay inside the mentioned always block.

Please correct my interpretation of the described scenario or confirm it. Also, I need to know if the division on zero behavior is defined in the SystemVerilog standard or depends on the simulator implementation.

Thanks in advance,
Hennawy

2

In reply to ahennawy:

This is an open issue. Specifically, the conversion of real -NAN (not a number) to an integer is not specified in the SystemVerilog LRM and it’s not clear if IEEE Std 754 Floating Point defines it.

Tools will either convert this to 0 or the largest integer, which is 0 as far a delay is concerned. Some tools produce a warning for either the divide by 0, or the delay conversion.