In reply to dave_59:
Regarding $rose((enable)[->k]); // k is a variable, consider using my package to handle dynamic repeats and delays.
https://verificationacademy.com/forums/systemverilog/sva-package-dynamic-and-range-delays-and-repeats
bit clk, a, b;
int k=2;
default clocking @(posedge clk); endclocking
// sequence definition from the package
sequence q_dynamic_repeat(q_s, count);
int v=count;
(1, v=count) ##0 first_match((q_s, v=v-1'b1) [*1:$] ##0 v<=0);
endsequence
ap_dyn: assert property(@ (posedge clk) a |=> q_dynamic_repeat($rose(b)[->1], k) );
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
- SVA Alternative for Complex Assertions
Verification Horizons - March 2018 Issue | Verification Academy - SVA: Package for dynamic and range delays and repeats | Verification Academy
- SVA in a UVM Class-based Environment
SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy