Hi, How can we generate valid parenthesis sequence using SystemVerilog constraints? Example: If length is 6, all of these valid combinations must be generated ()()(), ((())), (())(), ()(())

In reply to sjain12 : They are not always the same. item.index is a nested iterator within i. The constraint constraint c { foreach(parens[i]){ // can never have more close than open parenthesis in sequence parens.sum() with(item.index<=i? int'(item) : 0) >= 0; } …

In reply to akshataudpi : This is a fun interview question module top; class P; rand bit signed [1:0] parens[]; function new; parens = new[6]; endfunction constraint c { foreach(parens[i]){ // 1 is open, -1 is close parenthesis parens[i] inside {1,-1}; …

In reply to dave_59 : Hi Dave, which constraint can be used to avoid such as )(, )))(((, ()))(( ?

In reply to VE : // can never have more close than open parenthesis in sequence parens.sum() with(item.index<=i? int'(item) : 0) >= 0;

In reply to dave_59 : Dave, Why are you using int’(item) and not just item? TIA.

In reply to Verif Engg : It’s not strictly necessary as it is already implicit because of the RHS 0 in the conditional expression, but being explicit never hurts and is a good habit to keep.

In reply to dave_59 : Hi Dave, Could you please elaborate on how this is expanded into an equation? Isnt item.index is same as i? Thanks.

You have an amazing thought process!! Thanks for sharing the knowledge.

There is other question similar to above , check whether the given parenthesis is valid or not . I have implemented below using stack concept . module check_parentheses_stack; // Function to check if the parentheses sequence is valid using a stack function bit isValidParentheses(string seq); …

Hi @dave_59 , Is it not possible to simpify expression( parens.sum() with(item.index<=i? int'(item) : 0) >= 0; ) using simple function call inside constraints ? OR any other simple way ? Modified your code as below but output is coming wrong . please help me module top; class P; rand bi…

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Valid parentheses sequence

SystemVerilog

SystemVerilog, constraint-randomization

dave_59 August 18, 2025, 4:38pm 12

Getting Constraints are inconsistent and cannot be solved error.while generating prime number SystemVerilog

In reply to gsulliva: That is correct. Inputs to user defined functions get solved first, then the output of the function is used a constant value. The solver is not required to keep trying other input values to get an output value that meets a constraint on it.

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