The issue here is that, syntactically, the index is defined as a method of the iterator, not as a variable that can have bits selected. It should be a compiler error. The correct way to do this in SystemVerilog is to take a bit-select of a concatenation.
On revisiting the compilation error I see that constraint Sum_wo_Msb is legal
I am not clear on the reason behind using a concatenation operator and why is the expression considered legal with it
Section 7.12.4 of LRM says
Return type of the index method is an int for all array iterator items except associative arrays
Does {item.index} treat the int type result as a variable / packed array element?
Regarding [Q2] would it be correct to state that when resultant expression within the with() clause is non-integral or string type, it’s considered illegal
There’s a slight complication here because the 1800-2023 LRM introduced an enhancement along with (02735: Ballot Comment #48: Chaining of method calls - Accellera Mantis) that allows selecting bits […] of a function call. The LRM now supports bit/part selects of variables, concatenations, and the return value of a method call. Therefore, both item.index[0] and {item.index}[0] are valid and equivalent. However, it seems that tools have varying levels of support for either form.
You can use any valid types for the operator being used in the reduction. For instance, the sum() and product() operators can accept both real and integral types within the with() clause. On the other hand, the and(), or(), and xor() operators can only accept integral types.
Using bit-select of concatenation I observe that one tool throws the following Compilation Error
Error-[SCONCNA] Selection of concatenation not allowedtestbench.sv, 15tb,
"{item.index}[0]"
A selection of a concatenation is not allowed in constraint.
Whereas using bit-select directly on the iterator method throws Compilation Error saying ::
Bit or part select on function call is not yet implemented in constraints.