I am trying to bind interface to RTL module but I am not sure which one should I use to register it in UVM ?
one is uvmkit_register_bind_intf_vif
and the other is uvmkit_register_bind_intf_vif_inst
Here is a snippet code for this. In RTL side, we have a module defined as shown below.
RTL code :
module rs ( clk, rstb, valid, data );
...
endmodule
And there would be 4 instances for this module inside DUT (tb)
Here is top tb file :
module tb;
.....
rs rs0 (.clk(tb_clk), .rstb(tb_rstb), ....);
rs rs1 (.clk(tb_clk), .rstb(tb_rstb), ....);
rs rs2 (.clk(tb_clk), .rstb(tb_rstb), ....);
rs rs3 (.clk(tb_clk), .rstb(tb_rstb), ....);
.....
endmodule : tb
interface code :
interface my_intf ( input clk, input rstb, inout valid, inout[31:0] data);
clocking master_cb @(posedge clk);
input rstb;
output valid;
output data;
endclocking : master_cb
......
endinterface
bind code : (how to use uvmkit_register_bind_intf* to register these bind codes into UVM resource database ? )
bind rs:rs0 my_intf my_intf_inst0 (...)
bind rs:rs1 my_intf my_intf_inst1 (...)
bind rs:rs2 my_intf my_intf_inst2 (...)
bind rs:rs3 my_intf my_intf_inst3 (...)