UVMF: parametrized hdl typdefs

In reply to adrianf0:

I don’t see really the benefit of your approach. In any way your VIP has to be configured with respect to certain parameters etc. This package prrovides certain actual parameters for a configuration
It is an elegant way to use a package for this.
What you are doing is simple Verilog style, not knowing about packages.
If your common VIP packages is RO we can use this to perfrom a systme level setup by exporting imported names of packages.