Iam trying to understand UVM connect and have no knowledge on System C
I believe UVM connect is a methodology for a SystemC DUT.
Can this TB in UVM connect be re-usable for RTL DUT’s?
If Yes, what are the typical challenges/Issue we encounter and the advantage of UVM connect ?
2)Sorry for asking this but I dont understand what is this " integrate SV RTL models in System C"
I believe UVM connect is a methodology for a SystemC DUT.
Actually, UVM Connect is a class library that allows you to connect UVM SystemVerilog components to SystemC components. The SystemC side doesn’t have to be a DUT, but it could be. It could also be a reference model or just a “regular” verification component.
Can this TB in UVM connect be re-usable for RTL DUT’s?
That’s the beauty of UVM Connect, and the whole reason we created it. You can think of a UVM Connect environment as having three parts: 1) The UVM environment, 2) the SystemC environment, and 3) the SV/SC converter. To replace the SystemC side with an RTL DUT, you would remove the SystemC side, and replace the SV/SC converter with the appropriate UVM component (probably an agent) that has the same UVM interface as the SV/SC converter.
2)Sorry for asking this but I dont understand what is this " integrate SV RTL models in System C"
If your environment is primarily SystemC, you can integrate SV RTL models by creating a thin UVM Connect layer that allows your SystemC to send a transaction to a UVM driver that then converts that into pin-level communication with the SV RTL DUT.
Hope that helps.
Good luck,
-t