UVM 'uvm_info' usage

UVM
,
1

Hello all,
I tried below


(File A.sv)
module A;
   ...
   if(a=1) C=1;
   ...
endmodule



(File B.sv)
module B;
   ...
   if(b=1) C=1;
   ...
endmodule



(File TEST.sv)
`include "A.sv";
`include "B.sv";
module TEST();
  A A_1;
  B B_1;
  ...
  always @posedge C)begin
    `uvm_info(...)
  end
endmodule

Is there a way to display out which module(A or B) makes ‘C=1’
(e.g. I tried to use ‘uvm_info(“YES”, $sformatf(“%m”), UVM_LOW)’. Hoping to display like “A.sv(#line) @time ns: [YES]”)

Thank you,

2

In reply to podoroo:

I don’t think this has anything to do with `uvm_info, just general debugging skills. You need to give some more detail. If you know the values of an and b, you could then assume which module set C. But that involves explicit knowledge of how C is set. There are many debugging tools that can give you this kind of traceback information; there is nothing defined in the language to give you this.

3

In reply to podoroo:

In short, no. uvm_info() is just a fancy $display. If you want to trace signals and drivers, use a waveform tool.