Uvm test hang when adding #delay in sequence or driver

UVM
,
1

Hello,

I am having an unexpected behaviour when adding a Delay in my driver or in the sequence. After writing to a register i have to wait some time, i have tried adding a delay in my sequence after writing to the register, but the test hang at this point. I tried to add the delay in the driver before driving the stimulus so i would be waiting sometime before any write(waiting the last one to complete), but the test hangs at this point too.

Additionally i tried to add a second write to the same register just to add some delay, but the test hangs in the driver while waiting for the next clock cycle.

Like i am just debugging this issue and my DUT is not configured so it cannot received any stimulus, my test finishes right away after writing this register(if i don’t include any delay) and i am not able to see this write in my waveform, so i decided to include a Delay in my test run_phase before dropping the objection, but again it hangs at this point.

I have this same test bench fully working with a different register interface, i just made a copy of the functional tb and created a new UVC for the new register interface.

This is part of my virtual sequence:


class serdes_virtual_base_sequence extends uvm_sequence;
   `uvm_object_utils(serdes_virtual_base_sequence)

    virtual task body();
      h_chip_config = p_sequencer.h_chip_config;
      h_ds_config = p_sequencer.h_ds_config;
      config_reg();	    
      //config_cs();
      //config_ds();
      //generate_stimulus();
   endtask : body
//------------------------------------------------
   virtual task config_reg();
       `uvm_do_on_with(h_reg_write_seq,p_sequencer.h_reg_sequencer,{h_reg_write_seq.reg_addr_l == `SERDES_CNTRL_ADDR; h_reg_write_seq.reg_be_l == `SERDES_CNTRL_BE; h_reg_write_seq.reg_write_data_l == {29'h0, 3'b000};})
      `uvm_do_on_with(h_reg_write_seq,p_sequencer.h_reg_sequencer,{h_reg_write_seq.reg_addr_l == `TXEN_ADDR; h_reg_write_seq.reg_be_l == `TXEN_BE; h_reg_write_seq.reg_write_data_l == {25'h0, 7'h40};})

     **#100** //when adding this delay the test hangs
     //if i add this second write to this register or any other write or read the test hangs in the driver waiting for the next clock
     //**`uvm_do_on_with(h_reg_write_seq,p_sequencer.h_reg_sequencer,{h_reg_write_seq.reg_addr_l == `TXEN_ADDR; h_reg_write_seq.reg_be_l == `TXEN_BE; h_reg_write_seq.reg_write_data_l == {25'h0, 7'h40};})**
   endtask // config_reg
//------------------------------------------------
endclass : serdes_virtual_base_sequence

This is part of the driver:

class reg_driver #(int ADDR_WIDTH = 14, int DATA_WIDTH = 32) extends uvm_driver #(reg_seq_item #(ADDR_WIDTH, DATA_WIDTH));
  `uvm_component_param_utils(reg_driver#(ADDR_WIDTH, DATA_WIDTH))

//------------------------------------------  
  virtual task run_phase(uvm_phase phase);
    reset_dut_inputs();
    forever begin
      seq_item_port.get_next_item(req);
      drive_transfer(req);
      seq_item_port.item_done();
    end
  endtask : run_phase
//------------------------------------------------
  virtual task drive_transfer(reg_seq_item#(ADDR_WIDTH, DATA_WIDTH) seq_item);
    #100 **//when include this delay the test hangs here**
    set_dut_inputs(seq_item);
    populate_and_send_response_for_read_txn(seq_item);
  endtask : drive_transfer
//------------------------------------------------
  virtual task set_dut_inputs (reg_seq_item #(ADDR_WIDTH, DATA_WIDTH) seq_item);
    @(vif.dr_cb); **//when trying to write an additional register the test hangs here**
    #(h_reg_agent_config.pclk_period*0.1);
    vif.dr_cb.reg_write      <= seq_item.reg_write;
    vif.dr_cb.reg_read       <= seq_item.reg_read;
    vif.dr_cb.reg_addr       <= seq_item.reg_addr;
    vif.dr_cb.reg_be         <= seq_item.reg_be;
    vif.dr_cb.reg_write_data <= seq_item.reg_write_data;
  endtask : set_dut_inputs
//------------------------------------------------
endclass : reg_driver

Can anyone please give an idea why this is happening and how to debug the problem?
Thank you

2

In reply to jcaballero1987:

Dealing with Delay in the driver is not useful, because the delay will be mad in clock cycles. Add a certain number of clock cycles into your driver run_phase appropriate to your interface protocol.
Using Delay in your sequence is also not useful. The sequence is executed on the transaction level which does not know anything about timing. The order of the instructions is only relevant.

In your case your simulation might hang in the driver withh Delay.

3

In reply to chr_sue:

Hello chr_sue,

Thank you for your answer. I know that using Delay in sequence or driver is not the best practice but it is not the cause why the test is hanging. I removed the Delay in the driver and added 3 clock cycles wait(@(vif.dr_cb)) but the test hangs after the second cycle, like the third one never arrives, which it’s really weird given that the first two clocks did.

As I explained before the test hangs if i add a Delay in the run_phase of the test before dropping the objection, maybe this is not a good practice neither, but i am just trying to debug and figure out what is happening.

I have several functional UVM tb and i have tried adding delays in drivers, sequences and tests, just to see if they hang but they just run fine.
Any additional idea debugging this problem?

Thank you so much again

4

In reply to jcaballero1987:

What you have to look for is in the driver, if you get an item and you do item_done nd in the test if the sequence you have selected completes. Most easy way is to include `uvm_info.