UVM[SystemVerilog]:- Clarification regarding passing in line constraint

UVM
,
1

Hi,

I need to pass the value via inline constraint using same variable name. Like below.
**
Code:**

enum dev_t{TEST,TEST1};

class parent_seq extends uvm_sequence;
rand dev_t dev_t;
soft constraint {dev_t == TEST1;}
…

endclass

class seq extends parent_seq;
…
body()
$display(“%s”,dev_t.name()); ==> TEST1

endclass

class Seq1 extends parent_seq;
…
Body()
dev_t = “TEST”
$display(“%s”,dev_t.name()); ==> TEST
`uvm_do_with(seq, {seq.dev_t == dev_t; } )
endbody;

endclass:seq1

for above piece of code i am not getting proper value. we are expecting DEV_t should be TEST. But class seq print returning TEST1[soft constraint value not generated based on in line constraint value].

please correct me if any of above code is wrong…

Thanks,
selvavinayakam.na

2

In reply to selvavinayakam.na:

Your Code is not working as you are showing it.
The declaration of an enum is like this

enum {TEST,TEST1} dev_t;

dev_t is now a variable but not a type!

rand dev_t dev_t;

should result in an error, because dev_t as a type is not defined!
In you body task

dev_t = "TEST"

Is an initilization.

`uvm_do_with(seq, {dev_t == dev_t; } )

would be the right Syntax, which is confusing.

You should clean-up your code, defining an enumeration type and using a different Name for a variable of this type like this

typedef enum {TEST, TEST1} dev_t;

rand dev_t dev;
soft constraint {dev == TEST1;}