UVM & system verilog bind

UVM
,
1

Hi,
I have look around the forums, and understood how to use the bind feature (Which works great).

So I have an interface that i made bind to some module in the RTL,
currently this is using as a White-Box monitor.

Is there way to “write” this interface/bind into factory, so other components in UVM env
will also be able to get/work on same i/f?

As i said currently its only for White Box monitor,
but if i will want to add checkers etc, i need to have access enc/cfg/sequencer object etc…
So i think register the i/f into the factory will be best solution.

Thanks allot, Jony.

2

In reply to Jonyc:

I don’t know what you mean by,

i need to have access enc/cfg/sequencer object etc…

If you didn’t search the forum(s) for this topic, then I recommend doing so, there are many postings on this. Try searching on “bind interface internal” or something like that. Below are links I found in a couple of minutes that discuss binding to the DUT.

https://verificationacademy.com/resources/technical-papers/the-missing-link-the-testbench-to-dut-connection
http://www.sunburst-design.com/papers/CummingsSNUG2009SJ_SVA_Bind.pdf

The answer is YES, you can ‘set’ the interface in the config_db. Just make sure the handle of the interface in the ‘set’ method is:

<dut_top_inst>.<submodule_inst>.<interface_inst>

where, interface_inst is the bind instance from using something like:

bind  <submodule>   <interface_type>  <interface_inst>
3

In reply to dhserfer:

Can I access the elements from the bind instance?