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As UVM is becoming more ubiquitous, there is a high probability that it is (or definitely will be) used in your organization.
UVM is class-based and the methodology relies on monitors and scoreboarding along with data coverage as one main element of the verification process. -
In control-type of verification, the use of monitors and scoreboards tends to emulate RTL code, and that can be misleading; classes do not support concurrent assertions.
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In my White paper: “Using SVA for scoreboarding and TB designs” I demonstrate how assertions written in SystemVerilog interfaces with information provided by the drivers can be used to do this control-type of verification.
See http://SystemVerilog.us/papers/sva4scoreboarding.pdf
and a related issue at the Verification Academy the following paper
“Assertions Instead of FSMs/logic for Scoreboarding and Verification”
available in the verification-horizons October-2013-volume-9-issue-3
October 2013 | Volume 9, Issue 3 | Verification Academy
and “SVA in a UVM Class-based Environment”
SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
// For 10% discount, use code 45KJT5GN @ - A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115