+uvm_set_inst_override

UVM
, ,
1

hi:

I define a class:

clase mac_seq #(type T=mac_base_seq) extends mac_base_seq ;

`uvm_object_param_utils(T)

task body();

T Txq;
Txq = T::type_id::create(“txq”);
Txq.start(p_sequencer);
endtask

endclass
I Want to config the class type of Txq by the commandlinf of +uvm_set_inst_override=“mac_base_seq,mac_seq(#mac_base_seq_ext),test_seq_m”;
mac_base_seq is base class of mac_base_seq_ext.
But reprot Cannot register override for original type … in uvm_factory.
how to meet the requirement in the uvm?

2

In reply to birdluo:
The +uvm_set_inst_override switch only works with classes that have a string name associated with with the factory. The `uvm_object_param_utils macro does not register a class with a string name, it only does type based factory registration.

To make +uvm_set_inst_override work, you can do one of two things. Extend an un-parameterized class around your parameterized class and use that as your override:

class mac_seq_mac_base_seq_ext extends mac_seq(#mac_base_seq_ext);
`uvm_object_utils(mac_seq_mac_base_seq_ext)
...
endclass

Don’t use `uvm_object_param_utils to register your class with the factory. See Parameterized Classes, Static Members and the Factory Macros - Verification Horizons

3

In reply to dave_59:

the issue has be fixed after Extend an un-parameterized class;