Uvm sequence item - set_type_override()

UVM
,
1

Hi All,

I am trying to override a parameterized base sequence item with item which was inherited from the base class.
Base sequence item:
*class rra_item#(int REQ_WD = 16) extends uvm_sequence_item;
…
endclass

class rra_item_8 extends rra_item#(8);
…
endclass*

In the test case, The base item is overriden by inherited item by following way
function void build_phase(uvm_phase phase);
uvm_factory factory;
factory.set_type_override_by_type(rra_item#(16)::get_type(),rra_item_8::get_type());
endfunction : build_phase

The code compiles without an issue but during simulation, the simulator stopped due to BAD HANDLE REFERENCE

UVM_INFO @ 0: reporter [RNTST] Running test multi_req_test…

** Fatal: (SIGSEGV) Bad handle or reference.

Time: 0 ps Iteration: 7 Process: /uvm_pkg::uvm_phase::m_run_phases/fork#1847_2a9aa421b6c File: /stec/apps/mentor/questa_sim_10.4c/questasim/linux_x86_64/../verilog_src/uvm-1.1d/src/base/uvm_factory.svh

Fatal error in Function uvm_pkg/uvm_factory::set_type_override_by_type at /stec/apps/mentor/questa_sim_10.4c/questasim/linux_x86_64/../verilog_src/uvm-1.1d/src/base/uvm_factory.svh line 807

HDL call sequence:

Stopped at /stec/apps/mentor/questa_sim_10.4c/questasim/linux_x86_64/../verilog_src/uvm-1.1d/src/base/uvm_factory.svh 807 Function uvm_pkg/uvm_factory::set_type_override_by_type

called from /stec/proj/asic/cwm3/verification/users/mahi/rra_uvc/test.sv 80 Function rra_pkg/multi_req_test::build_phase

Please help me to get rid of this error.
Thanks in Advance.

2

In reply to dmahendran:

You declared a variable
factory, but you never initialized it with a handle to the global factory. But there’s no need to do this as uvm_component already has this method. So call
set_type_override_by_type() directly.

3

In reply to dave_59:

Hi Dave,

Thank you for a quick and appropriate reply. It solved the above-mentioned issue.
but i am getting into “type casting issue”.
_
The code changed:_
virtual function void end_of_elaboration();
set_type_override_by_type(rra_item#(16)::get_type(),rra_item_8::get_type());
endfunction : end_of_elaboration
_
sequence declaration:_

*class multi_req_seq extends uvm_sequence#(rra_item#(16));
uvm_object_utils(multi_req_seq) uvm_declare_p_sequencer(rra_sequencer_t)

function new(string name="");
  super.new(name);
endfunction : new

task pre_start();
  `ifdef UVM_POST_VERSION_1_1
      uvm_phase starting_phase = get_starting_phase();
  `endif
  if(starting_phase != null)
     starting_phase.raise_objection(this);
endtask : pre_start

task body();

  for(int i=0; i< 20; i++) begin
    `uvm_do(req);
  end

endtask : body

task post_start();
ifdef UVM_POST_VERSION_1_1 uvm_phase starting_phase = get_starting_phase(); endif
if(starting_phase != null)
starting_phase.drop_objection(this);
endtask : post_start

endclass : multi_req_seq*

the simulator shows the following error message,
*####

UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(272) @ 0: reporter [Questa UVM] End Of Elaboration

** Error: (vsim-3971) $cast to type ‘class work.rra_pkg::rra_item #(16)’ from ‘class work.rra_pkg::rra_item #(8)’ failed in file /stec/proj/asic/cwm3/verification/users/mahi/rra_uvc/rra_seq_lib.sv at line 64.

Time: 0 ps Iteration: 50 Region: /uvm_pkg::uvm_sequence_base::start

UVM_FATAL @ 0: uvm_test_top.o_rra_env.o_rra_agent.o_rra_sequencer@@seq [NULLITM] attempting to start a null item from sequence ‘uvm_test_top.o_rra_env.o_rra_agent.o_rra_sequencer.seq’

#*

can you please point me out what i am missing here?

Thanks
Mahendran

4

In reply to dmahendran:

rra_item_8 is extended from rra_item#(8). You can’t use that as an override of rra_item#(16).

5

In reply to dave_59:

Thank you Dave. It solves my problem. Do you have an example for creating parameterized uvc ?