UVM ScoreBoard to check bit matching

UVM
,
1

Hello,

I need to build a  UVM ScoreBoard for verifying a DSP Block.

DSP Block has 5 stages IQSamples(UVM Agent) → Mixer(DUT) → Filter (DUT} → Quantizer {DUT} ----> Memory {DUT}
CModel give the IQSamples to be sent to Mixer Stage.
IQSamples are driven from UVM Agent in the Testbench.
Outputs of all stages like Mixer,Filter,Quantizer and Memory are given by CModel.
I need to compare each stages of RTL with corresponding files from CModel to do bitmatching.

I do not have a Reference Model for the DSP Block.  I plan to build different Queues in ScoreBoard

by reading the CModel files of Mixer, Filter, Quantizer and Memory. Mixer[], Filter[], Quantizer[] and Memory]]

The issue here is Scoreboard is a class and it cannot monitor the Verilog DUT ouputs of Mixer, Filter and Quantizer.

Does that mean , I cannot use a UVM ScoreBoard in this scenario.

One thing I can do is Build a Verilog Checker, where the Checker read the contents of the CModel files and

compare the outputs of DUT by doing hierarchical compare like

 if ( CModel !==  tb.dut.mixer.output )  $display (" ERROR BitMatch Fail " );  <---  This is not a UVM style

What is the UVM way to Build a ScoreBoard to do Bitmatch in this scenarion

UVM Experts who has done this type of DSP Verification , Please help

Thanks
JeffD

2

In reply to dvuvmsv:

You can build passive UVM Agents for each internal interface and pass the interface handle to the monitor of these Agents. Start collecting the output in the monitor and feed it to your TB scoreboard using TLM ports.

3

Hi Sam,

Thanks for your reply. These are internal RTL Signals.
How can you build passive UVM agents from internal RTL signals ?
Suppose the internal signals are
tb.dut.mixer.I[4:0]
tb.dut.mixer.Q[4:0]
tb.dut.mixer.enable
tb.dut.mixer.clk

How can you define an interface with these internal RTL Signals ?

Thanks
JeffD

4

In reply to dvuvmsv:

SV provides you the bind construct to access any internal signal in your RTL code. See the SV Language Manual for more details.

5

Thanks chr_sue. I found a related post here.
https://verificationacademy.com/forums/systemverilog/how-bind-inner-signals-dut