Uvm_resource_db

I need to pass a clk_period value via from a test to clk_period check assertion in top module via uvm_resource_db.
Please let me know what is wrong in this code

test :


class test_x_basic extends base_x_test;
   realtime time_period;
  `uvm_component_utils(test_x_basic)

  function new (string name ="test_x_basic", uvm_component parent =null);
    super.new(name,parent);
  endfunction
  virtual function void build_phase(uvm_phase phase);
    begin
      uvm_resource_db #(realtime)::set("CLK_PERIOD", "time_period", 6);
      set_type_override_by_type(soc_virtual_seq::get_type(),test_x_basic_seq::get_type());
      set_type_override_by_type(soc_config::get_type(),test_x_basic_config::get_type());
      super.build_phase(phase);
    end
   endfunction
endclass

top module


module tb_top ();

realtime clk_period;
initial
 begin
    #0;
    uvm_resource_db #(realtime)::read_by_name("CLK_PERIOD","time_period", soc_tb_top.clk_period);
   //if(!uvm_resource_db #(realtime)::read_by_name("CLK_PERIOD","time_period", clk_period,this))
   // `uvm_fatal("read_y_name failed for resource in this scope");
    run_test();
 end 


`ifdef ASSERT_CHECK_EN
   `include "list_of_clk_assertion.sv"
 `endif

list_of_assertion.sv


bind top.xyz clk_freq_check pclk_check (pclk,rstn, tb_top.clk_period,0,0,0,500,"pclk");

clk_period above is not picking the value given from test

In reply to kesav_abj:

You are setting tim_period in your test. And you are trying to read this value in the toplevel module before you are constrcting the test. This will not work.
run_test is constrcting your whole UVM environment.
BTW you should never use the resource_db. Instead use the uvm_config_db.

In reply to kesav_abj:

Try using uvm_wait_for_nba_region() instead of #0 in tb_top. It should work.


initial uvm_pkg::run_test();

initial begin
  uvm_pkg::uvm_wait_for_nba_region(); //#0;
  .
  .
  .
end

Note that it should be called in parallel with run_test().

uvm_wait_for_nba_region : Callers of this task will not return until the NBA region, thus allowing other processes any number of delta cycles (#0) to settle out before continuing.