UVM register report ：unknown access right

UVM
,
1

Hi,

I am planing to switch UVM1.1b to UVM1.1d, there is a error about using uvm register access.

this is my code, I want to map HPIRQLTCH_reg to this address 32’h00000028 ,and the access right is “W1C”
SW_MAP.add_reg(HPIRQLTCH_reg, 32’h00000028, “W1C”);

when I use UVM1.1B, no error
but when I use UVM1.1d, Questasim will report below error:
UVM_ERROR verilog_src/uvm-1.1d/src/reg/uvm_reg_field.svh(955) @ 0: reporter [RegModel] Register ‘reg_rm.HPIRQLTCH_reg’ containing field ‘PPSINT0’ is mapped in map ‘reg_rm.SW_MAP’ with unknown access right ‘W1C’

if I change “W1C” to “RO”, there is no error, why add_reg can not have “W1C” attribute?

Best Regards
Adams

2

You have to differentiate between register access rights and register field access rights. An entire register can only be made RW, RO, WO from a certain address map. Fields can contain a wide variety of access permissions (like W1C). What you see there is (most probably) a bug in UVM 1.1b that wasn’t flagging an error when you were adding the register.