Uvm register field model for 512bytes and two levels downthe hierarchy there many subfield and so on,

UVM
,
1

Hi,

I am having register size of 512 bytes (lets say ext_abc is a register). there are several fields configured for ext_abc register and field has bit wise sub fields. lets say ext_csd(512 bytes)–> kl_ext_abc_field(1 byte),mn_ext_csd_field(4 bytes),xy_ext_csd(16bytes). and each of these fields further has bit wise fields like lets say for mn_ext_csd_field → bit[0]=support,bit[4:1]implementation and remaining bits reserved.
here my question is how to uvm register model for such kind of registers/scenarios.

any help on this will be appreciated.

Regards,
ram

2

In reply to hiramana:

hi,

just to get it correct you do have a register structure like this:

Register
  +---- Field
  |        +--- subfield
  |        +--- subfield
  |        +--- subfield
  |        +--- subfield
  +---- Field
  |        +--- subfield
  |        +--- subfield
  |        +--- subfield
...
...

If the above assumption is correct then you would need a class structure like this:



Register -> uvm_reg_block
  +---- Field -> uvm_reg
  |        +--- subfield -> uvm_reg_field
  |        +--- subfield -> uvm_reg_field
  |        +--- subfield -> uvm_reg_field

It is a bit tricky naming wise as UVM uses different names for the different levels but
as I see it UVM would consider your registers to be a register block and your first
level of subfields to be the register and your last level of subfields to be your fields.

I hope this helps.

Bye