Uvm reg read from uvm-monitor

In reply to yuvraj khare:

A monitor is assigned to be a passive component. You are violating this rule by using a read to the RAL. In the testbench you need only a get. The get takes the register value from the mirror in the testbench. The read is doing a read through the bus interface and a get.
I’m wondering why you are observing your interrupt in the monitor. Finally you have to start in case of an interrupt an interrupt sequence. This happens in the sequencer. How do you send the interrupt information to the sequence/sequencer? There is no standard interface. You have to implment this on your own.
Why do you not use the existing interface betwenn the driver and the sequencer?
How to implement is you can see in a code example of the Verification Academy.
Code Example Downloads | Verification Academy, interrupts - simple.