In reply to sa5691:
In reply to yuvraj khare:
If possible show the entire code, it is very difficult to figure out what is going wrong with just 2 lines of code.
class Interrupt_monitor extends uvm_monitor;
`uvm_component_utils(Interrupt_monitor)
bit [31:0] interrupt_mask;
ral_sys_model regmodel;
virtual prot_if prot_vif;
extern function new(string name, uvm_component parent);
extern function void build_phase (uvm_phase phase);
extern task run_phase (uvm_phase phase);
extern task interrupt_service ();
extern task interrupt ();
endclass : Interrupt_monitor
function void Interrupt_monitor::build_phase (uvm_phase phase);
super.build_phase(phase);
if(!uvm_config_db#(virtual prot_if)::get(this,“”,“prot_vif”,prot_vif))
uvm_fatal(get_type_name(), $sformatf("Unable to get prot_vif from cfg database")) if (!uvm_config_db #(ral_sys_model)::get(null,get_full_name(),"regmodel",regmodel)) uvm_fatal(get_type_name(), “Unable to get the regmodel from cfg database”))
endfunction : build_phase
task Interrupt_monitor::run_phase (uvm_phase phase);
super.run_phase(phase);
forever begin
fork
begin
interrupt_service();
end
join
end
endtask :run_phase
task Interrupt_monitor::interrupt_service();
fork
begin
sys_interrupt();
end
begin
count = count+1;
end
join_any
endtask :interrupt_service
task Interrupt_monitor::sys_interrupt();
fork
begin //{
if(top_cfg.interrupt_mask != 32’h0) begin
while(interrupt_status == 0) begin
regmodel.reg_bank.REG_ISR.read(status,interrupt_status);
end
if(interrupt_status | hxtop_cfg.intr_enable == hxtop_cfg.intr_enable)
uvm_info(get_type_name(), $psprintf("Interrupt status is set for correct interrupt "), UVM_NONE) else uvm_info(get_type_name(), $psprintf("Interrupt status is not for correct interrupt "), UVM_NONE)
end
end //}
begin //{
if(interrupt_mask == 32’h0) begin //{
case(top_cfg.intr_enable)
32’h0000_0000: begin
wait(prot_vif.interrupt != 0);
end
32’h0000_0040: begin
wait(prot_vif.interrupt[4] != 0);
end
endcase
join_any
endtask : sys_interrupt