Uvm reg read from uvm-monitor

In reply to chr_sue:

In reply to yuvraj khare:
Could you please show some more code from your monitor?
And I’d like to ask you what are you doing with the read register value in the monitor?

Basically it is Interrupt monitor, so am reading the status of interrupt (if interrupt is mask) i.e. using RAL model
if(top_cfg.interrupt_mask != 32’h0) begin
while(interrupt_status == 0) begin
regmodel.reg_bank.REG_ISR.read(status,interrupt_status);
end
Getting an error where am using the reg model.
Please let me know!