hie, i am working on a project where i am adding two DUTs instead of existing one. The uvm environment which was existing here, had one reg model. now since i have two DUTs with different base address, i need to have two different reg models in the same environment. how can i create two different reg models. the offset address for all the registers will be same in the second model also, only thing to be changed is the base address.
In reply to tarungupta:
There are multiple approaches. But I would like to suggest the following one.
- Extend a class from uvm_reg_block and take both reg model instances
- Configure both with separate base addresses.
- Take top reg_block instance and perform all register read/write operation with absolute hierarchies.
I feel, this approach will provide reusability from block to chip-level verification.
Regards,
Mitesh Patel
In reply to tarungupta:
hie, i am working on a project where i am adding two DUTs instead of existing one. The uvm environment which was existing here, had one reg model. now since i have two DUTs with different base address, i need to have two different reg models in the same environment. how can i create two different reg models. the offset address for all the registers will be same in the second model also, only thing to be changed is the base address.
Waht do you mean with ‘2 DUT’. Generally you have 1 RTL toplevel… Do you have 2 instances of the same design in your DUT or what is it? If the register access is different there might be also differences between both DUTs. This would require also an extended UVM testbench.