UVM Reg Model & String Issue

UVM
1

Hi Everyone,
I have the following piece of code, which on compiling, error is shown.


task vl_group_interrupt(bit [2:0] grp_no);
   bit [31:0] grp_addr;
   bit [31:0] grp_data;

   string reg_name = $psprintf("reg_model.abc_es_global_regs.es_global.TX_VL_GROUP %0d _INT_STATUS",grp_no);

   reg_name .read(status,grp_data,.parent(this));

   vl_interrupt(grp_data,grp_no,1);
endtask

Got the below error while compiling.

reg_name.read(status,grp_data,.parent(this));
|
*E,QAANBI (/proj/arinc664/users/mafsar/wa1/HIDA/verif_ip/bench/sequences/afdx_es_interrupt_seq_lib.sv,138|21): This is not a valid built in method name for this object. [SystemVerilog].
EOF

Is there any way to overcome above error?.
2

The variable reg_name is a string and only contains the methods appropriate for a string. You can’t use a string as another type of variable.

You will need to reference the register directly, or if you want to be flexible, you can use a string-based lookup to get the register.

3

In reply to cgales:

The variable reg_name is a string and only contains the methods appropriate for a string. You can’t use a string as another type of variable.
You will need to reference the register directly, or if you want to be flexible, you can use a string-based lookup to get the register.

Maybe Same question

When I ran the below code I got failed in other tool but Questa.


module top;
  string s = "test[0]";
 
  initial begin
    if(s.match(".*[\\d].*") ) $display("MATCH");
    else $display("NOMATCH");
  end
endmodule

~
I got the below message

QuestaSim-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
Start time: 10:31:34 on Dec 05,2022
vlog -writetoplevels questa.tops -timescale 1ns/1ns design.sv testbench.sv 
-- Compiling module top

Top level modules:
	top
End time: 10:31:35 on Dec 05,2022, Elapsed time: 0:00:01
Errors: 0, Warnings: 0
# vsim top -batch -do "vsim -voptargs=+acc=npr; run -all; exit" -voptargs="+acc=npr" 
# Start time: 10:31:35 on Dec 05,2022
# ** Note: (vsim-3812) Design is being optimized...
# //  Questa Sim-64
# //  Version 2021.3 linux_x86_64 Jul 13 2021
# //
# //  Copyright 1991-2021 Mentor Graphics Corporation
# //  All Rights Reserved.
# //
# //  QuestaSim and its associated documentation contain trade
# //  secrets and commercial or financial information that are the property of
# //  Mentor Graphics Corporation and are privileged, confidential,
# //  and exempt from disclosure under the Freedom of Information Act,
# //  5 U.S.C. Section 552. Furthermore, this information
# //  is prohibited from disclosure under the Trade Secrets Act,
# //  18 U.S.C. Section 1905.
# //
# Loading sv_std.std
# Loading work.top(fast)
# 
# vsim -voptargs=+acc=npr
# run -all
# MATCH
# exit
# End time: 10:31:36 on Dec 05,2022, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0

But when I ran with other tool, then I got error.
Is this Tool specific problem?

4

In reply to UVM_LOVE:

This question is unrelated to this topic. Please start it as a new question, especially then the topic has been dormant for many years.

The match method is an enhancement to SystemVerilog not available in all tools.