UVM Reg Model for 32 bit IP interface from 8 bit interface

UVM
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Hi,

At the chip level we have 8 bit interface, and at the IP level we have 32 bit interface!!!
How can we achieve the UVM reg for 32 bit register using 8 bit interface as at a time from reg model only 8 bit data is send!!!

Any example will be helpful?

Regards
Taahir

2

In reply to syed taahir ahmed:

Can you clarify the problem (what do you mean by “IP”)? Is it UVM Verification IP or RTL?

Without fully understanding your specific scenario, I would suggest looking at n_bytes in the create_map function (if you haven’t already). If the bus width mismatches are solely in RTL and the RTL register must be updated 32-bits at a time, then that is an RTL bug.

3

In reply to dhserfer:

In reply to syed taahir ahmed:
Can you clarify the problem (what do you mean by “IP”)? Is it UVM Verification IP or RTL?
Without fully understanding your specific scenario, I would suggest looking at n_bytes in the create_map function (if you haven’t already). If the bus width mismatches are solely in RTL and the RTL register must be updated 32-bits at a time, then that is an RTL bug.

Hi , Actually it’s RTL of the IP.

I think it’s not an bug, it’s implementation at RTL IP which had 32 but interface and at the chip level we only have 8 but interface.

Regards
Taahir

4

In reply to syed taahir ahmed:

If the 32-bit RTL register does not behave correctly with an 8-bit R/W access then it is an RTL bug (it’s a matter of semantics, but a design flaw is still a bug from the verification point of view).

If you can update the register with 8-bit accesses then set n_bytes to “1” in the create_map method. Otherwise it requires an RTL fix (matching bus widths, or some sort of bridge or glue logic that builds a 32-bit access out of 4 8-bit accesses).

5

In reply to dhserfer:

In reply to syed taahir ahmed:
Can you clarify the problem (what do you mean by “IP”)? Is it UVM Verification IP or RTL?
Without fully understanding your specific scenario, I would suggest looking at n_bytes in the create_map function (if you haven’t already). If the bus width mismatches are solely in RTL and the RTL register must be updated 32-bits at a time, then that is an RTL bug.

Thanks , I’ll look in to it further and come back for the questions.

Regards
Taahir

6

In reply to syed taahir ahmed:

Hi Taahir,

I am assuming there is an interconnect that downsizes the 32-bit register access to an 8-bit access at the system level.

I don’t think there is an easy way in UVM REG to downsize a 32-bit txn to an 8-bit txn. I would modify the driver to accept a 32-bit txn and split it into 4 beats while driving the bus.

Thanks,
Muffadal

7

In reply to muffadal-l:

In reply to syed taahir ahmed:
Hi Taahir,
I am assuming there is an interconnect that downsizes the 32-bit register access to an 8-bit access at the system level.
I don’t think there is an easy way in UVM REG to downsize a 32-bit txn to an 8-bit txn. I would modify the driver to accept a 32-bit txn and split it into 4 beats while driving the bus.
Thanks,
Muffadal

Hi Muffadal,

Correct i think i should look in to the approach you suggested.
Also how about Back door approach?

Regards
Taahir

8

In reply to syed taahir ahmed:

Hi Taahir,

It depends on what you are trying to achieve. If the goal is to initialize the registers with certain set of values you can use the backdoor approach.

Thanks,
Muffadal