Uvm_reg_mem_built_in_seq read value and mirrored value is not matching because of reset

[Abuzar_Gaffari]

I am starting this built in sequence, at the end of the sequence I am getting 3 error for 3 registers. One of them is
regmodel.REG_0" value read from DUT (0x00000000fffffffe) does not match mirrored value (0x0000000000000001)

the reset value to that register is all 0000001. how is this reset getting applied in between? I have called regmode.reset(); inside run_phase of testcase before starting the sequence.

I feel there is some synchronization issue. but don’t know exactly what.

If I assume reset is being applied by sequence, then dut read value should be 00000001 and mirrored value should be 00000001. but here dut read value is not 00000001. Correct me if I am understanding wrong.

Anyone knows the answer?

[chr_sue]

It is near impossible to answer your question without seeing more code. It looks like your RAL fegister did not get updated. The most simple way to check this is to execute an ‘update’ prior to READ. And you should execute your register reset from the sequence.

[Abuzar_Gaffari]

Thanks @chr_sue for the reply.
I have figured out the solution, issue was with the hdl_path, hdl_path was mapped to a config_register but apb interface was dealing with reg_q register. This reg_q register was connected to config_register.
I have attached the diagram for clear understanding.